Multilayer Ceramic Chip Capacitors

TDK item description  ?
C2012JB0J685MT****
Applications
Commercial GradeCommercial Grade
Feature
GeneralGeneral (Up to 50V)
Series
C2012 [EIA 0805]
Status
ObsoleteObsolete
Discontinue Issue Date : Apr.28, 2016
Last Purchase Order Date : Dec.31, 2016
Last Shipment Date : Mar.31, 2017

Images are for reference only and show exemplary products.

Size

Length(L)
2.00mm ±0.20mm
Width(W)
1.25mm ±0.20mm
Thickness(T)
1.25mm ±0.20mm
Terminal Width(B)
0.20mm Min.
Terminal Spacing(G)
0.50mm Min.
Recommended Land Pattern (PA)
1.00mm to 1.30mm(Flow Soldering)
0.90mm to 1.20mm(Reflow Soldering)
Recommended Land Pattern (PB)
1.00mm to 1.20mm(Flow Soldering)
0.70mm to 0.90mm(Reflow Soldering)
Recommended Land Pattern (PC)
0.80mm to 1.10mm(Flow Soldering)
0.90mm to 1.20mm(Reflow Soldering)

Electrical Characteristics

Capacitance
6.8μF ±20%
Rated Voltage
6.3VDC
Temperature Characteristic  ?
JB(±10%)
Dissipation Factor (Max.)
10%
Insulation Resistance (Min.)
14MΩ

Other

Soldering Method
Wave (Flow)
Reflow
AEC-Q200
No
Packing
Blister (Plastic)Taping [180mm Reel]
Package Quantity
2000pcs

Characteristic Graph (This is reference data, and does not guarantee the products characteristics.)